FIG. 1 shows the block diagram of the electrical system 1 of a typical winchester disk drive storage subsystem, having a host interface 5, a disk interface 2-4, a serial interface 8, a microcontroller 10, a microcontroller data bus 6, a microcontroller address and control bus 7, a non-volatile semiconductor memory such as an Electrically Programmable Read Only Memory (EPROM) 20 for storing code executed by the microcontroller and, a code/data RAM 30 for storing parameters, and variables used by the microcontroller 10. A typical Winchester disk array storage system may also have a Controller 40, a local buffer RAM 50, a R/W Channel 60, a Motion Control 70, a Servo Driver 81, and a Motor Driver 82. The controller 40 includes a host Interface Control 41, Buffer Control 42, Sequencer 43, Error Checking and Correction (ECC) 44 and a first micro Interface 45. The Motion Control 70 includes a Servo Control 71, a Motor control 72, and a second micro Interface 73.
The local buffer RAM 50 is used for temporary storage of data between the host and storage system add and if the storage subsystem employs caching, then also for storage of cached data of the storage subsystem. The local buffer RAM 50 must support a bandwidth that allows the concurrent transfer of data from host, disk, ECC and the microcontroller. The buffer control 42 controls access to the local buffer 50, by different utilization devices, namely host, disk, on the fly correction circuitry of the ECC, and the microcontroller 10.
With the continuous increase in the disk transfer rates and the transfer rate at the host interface, the local buffer RAM must support higher bandwidth. The ATA-2 standard requires host transfer rates up to 22 Mbyte/sec. The SCSI-2 standard requires host transfer rates of 10/20 Mbytes/sec (8-bit SCSI bus/16-bit SCSI bus) and proposed UltraSCSI standard requires host transfer rates of 20/40 Mbytes/sec (8-bit SCSI bus/16-bit SCSI bus). The disk transfer rates are increasing to 10-20 Mbytes/sec. Therefore the local buffer RAM must support bandwidths of 20-60 Mbytes/sec. In the prior art in order to increase the buffer bandwidths, the size of buffer RAM data bus is increased to 16 or 32 bits. Bandwidths up to 40 MBytes/sec can be achieved with commercially available DRAMs having 16 bit data bus.
The code/data RAM 30 is used for storing parameters and variables used by the microcontroller firmware. It can also be used to store part of the firmware code that is executed by the microcontroller 10. A drawback of storing code only in ROM is that once ROM or EPROM is programmed, making changes is costly and requires scrapping ROMs which have been previously manufactured. Executing code from RAM provides the flexibility of making changes and/or additions to the code. In systems that execute code from RAM, the microcontroller executes the code from a boot ROM during power-on initialization to load the RAM with code which is stored on the storage media itself.
To reduce the cost of the electrical system of the storage subsystem, it is desirable to combine the local buffer RAM 50 with the code/data RAM 30. The ProDrive Low Profile Series 270/340/540 of 3.5-inch hard disk drives for AT and SCSI bus from Quantum Corporation employs an architecture in which the code/data RAM is combined with local buffer RAM, and the code/data used by the microcontroller (previously stored in a separate RAM) is also stored in the local buffer. In these drives the maximum disk transfer rate is 46 Mbits/sec. The drives for AT bus support ATA transfer rates of 6 Mbytes/sec in PIO mode and 13 MBytes/sec in Fast Multiword DMA mode. Drives for SCSI bus support transfer rates of 10 MBytes/sec in synchronous mode. In these drives, a conventional 64K.times.16 DRAM (part # TC511664) is used for local buffer RAM where 32K bytes of the RAM is used to store code used by the microcontroller.
As mentioned earlier and also evidenced by the performance of these drives, the conventional memories can not meet the requirements of a cost effective high performance storage subsystem.
A major improvement can be made if the microcontroller access and the access coupled through a buffer controller from other independent utilization devices (such as disk interface, host interface control) are separated.
Application specific multiport memories have been developed for serial scan applications such as video display systems which combine a DRAM with an on-board Serial Access Memory (SAM).
FIG. 2 shows an application specific memory according to U.S. Pat. No. 4,541,075, by Dill et al. having a row buffer register which can transfer rows of data to and from the main memory and a second Input/Output port for accessing the row buffer register in either serial or parallel mode. A limitation of the memory device described in this patent is that only one utilization device can independently use the second I/O port. Yet another limitation of the memory device proposed by Dill et al. is that partial write or masked write (writing only to selected words) from the row buffer register to a row of the main memory is not supported. In this memory device, the partial write can be emulated by "memory row read modify write" operation which includes the steps of: transferring the row from the main memory to the row buffer register, modifying the row buffer register through the second I/O port, and transferring the row buffer register back to the row of the main memory. This "memory row read modify write" operation assumes that the data of the same row in the main memory was not changed between the read and write back. Note that data corruption will occur if during "memory row read modify write" operation, part of the data in the main memory row was modified through the first I/O port. This is a general limitation of the prior art and will be discussed in more detail below.
Utilization or peripheral devices generally access a semiconductor memory through the memory's ports. Accesses by multiple utilization devices therefore require the semiconductor memory being accessed to have multiple ports to support independent utilization device accesses. A major limitation in providing access by multiple independent utilization devices through a dedicated port per utilization device is that concurrent write to the same row of the memory by two or more utilization devices is not possible without comprimising integrity of the data. FIG. 3 shows an extension of the memory device taught by Dill et al. In this patent further having a third I/O port for accessing a second row buffer independent of the first row buffer for use by a second utilization device. FIG. 4 shows two blocks in the main memory wherein the tail end of block 1 and beginning of block 2 are in the same row of the main memory (row 2). Consider an application in which the first utilization device is using first row buffer register through second I/O port and a second utilization device is using the second row buffer register through the third I/O port; and furthermore utilization device 1 is accessing block 1, and utilization device 2 is accessing block 2. Now consider the following sequence of operations in this example: utilization device 1 reads row 2 of the memory into the first row buffer register and starts modifying the first row buffer register through the second I/O port, utilization device 2 read the same row of memory into the second row buffer register and starts modifying the second row buffer register through the third I/O port, utilization device 1 completes modifying the beginning of the row buffer register which is part of block 1 and writes it back to the row of the memory, utilization device 2 completes modifying the tail end of the second row buffer register which is part of the block 2 and writes it back to the row of the memory. It should be apparent that the last operation will then overwrite the data of block 1 which was modified by utilization device 1 and causes data corruption.
Yet another data corruption resulting from "memory row read modify write" operation unique to storage subsystem applications will be discussed next. Consider an execution of a read command by the storage subsystem during which blocks are read from the disk and disk interface (first utilization device) will be writing blocks of data to the memory, and concurrently good blocks which are buffered in the memory are read by the host interface (second utilization device). During this operation if an error occurs when a block is read from the media and transferred from disk interface to buffer, then the on-board "on the fly correction (OFC)" circuitry of the ECC will attempt to correct the correctable errors concurrent with the transfer of the next block from the disk interface. The case in which the error was located at the tail end of the blocks, which is in the same row of the memory as the beginning of the next block, will be considered. This case may use the following sequence of operations: utilization device reads the row of the memory into the first row buffer register and starts modifying the first row buffer register through the second I/O port, the OFC circuitry locates an error in the same row of the memory and corrects the error through the first I/O port, utilization device completes modifying the tail end of the row buffer register which is the beginning of block and writes it back to the row of the memory, which will then overwrite the data which was corrected by the OFC circuitry and cause data corruption.
These types of a problems, in order to be avoided, place a restriction on memory utilization such that if a subset of memory rows are dedicated for each block, which requires that either the data block to be multiple of a row size (which may not be always possible) or waste some part of the memory.
Furthermore, multiple parallel-by-bit I/O ports each coupled to a utilization device increases the number of the pins of the memory device package, which increases the cost of the memory device.
There is a need for a cost effective high performance multiport memory for block access applications such as disc drive applications that allows independent access by multiple utilization devices coupled through a buffer controller to a second parallel-by-bit I/O port.